1. Field of the Invention
The present invention relates in general to an electro-optical liquid crystal display suitable for finely graded operation and methods of driving and manufacturing the same.
2. Description of the Prior Art
Recently, thin film transistor liquid crystal displays (TFTLCD for short) have been increasingly broadly utilized, along with the development of color liquid crystal displays, rather than simple matrix type liquid crystal displays because the former type is particularly excellent in terms of brightness, contrast and wide view angles.
FIG. 1(A) is a circuit diagram showing a driving circuit for controlling one pixel of such a TFTLCD. As shown in the figure, a single thin film transistor is provided for the pixel located at each intersection of a matrix diagonal wiring comprising horizontal addressing lines (only one line VG being illustrated) and vertical data lines (also only one line VD being illustrated). The drain (D) of the transistor is connected to the corresponding one of the data lines while the source (S) thereof is connected to the corresponding one of the electrode pads defining pixels of the display (not shown). The gate of the transistor is connected to the corresponding one of the addressing lines VG. Such a matrix type design has been broadly employed already in the DRAM technique so that the reliability thereof is believed to have been fully established. In the case of the driving technique for liquid crystal display, however, there remain still several problems to be solved since the operation of liquid crystal displays includes also analog data manipulation.
FIG. 1(B) is a schematic diagram showing examples of signals applied to the addressing line VG and the data line VD and the resultant driving voltage at the electrode of the corresponding pixel in response to the signals. If a liquid crystal material is subjected to a DC voltage for a substantial time period, the characteristics of the materials are degraded. The signal at the data line therefore is periodically inverted (usually for each frame) in order to invert the direction of the voltage applied across the liquid crystal material.
The mechanism of the operation of the pixel is next explained. When a voltage pulse is applied to the gate, the transistor is turned on in order to transmit electric charge to the electrode pad of the pixel from the data line being at a high level so that the voltage level of the electrode pad is increased (region t1). The increase, however, is not so fast. In the case the transistor is made of an amorphous silicon semiconductor, the mobility of carriers is so low that the pulse applied to the gate is sometimes removed and the transistor is turned off before the voltage at the pixel reaches to the necessary level. In the case that the transistor is made of polysilicon, such undesirable situation is substantially improved. If the operational speed is so high that the pulse width is narrower than one microseconds, however, even the polysilicon transistor can no longer follow such a high speed. It takes 30 milliseconds in usual cases to scan one frame. The pulse width of the addressing signal is therefore about 50 microseconds in the case that the number of the addressing lines is 480 (480 rows display). If higher definition of grading is desired, however, the pulse width narrower than one microsecond becomes necessary.
The voltage at the pixel then drops by xe2x80x9cV. This drop, called xe2x80x9creboundxe2x80x9d, is caused by charge accumulated in the parasitic capacitance which is formed by the overlap between the gate electrode and the source region. The voltage drop increases as the parasitic capacitance increases. In the case of displays utilizing amorphous TFTs, a capacitance is provided across the liquid crystal at the pixel in order to reduce the voltage drop. The provision of such a particular capacitance, in turn, increases the load of the TFT and the other peripheral circuit and decreases the aperture ratio because of the wiring for the capacitances so that the brightness is decreased.
In the case of polysilicon transistors, such a problem of the voltage drop is not so significant since the self-alignment process can be employed for forming the gate electrode and the source and drain regions. The voltage drop, however, still exists as high as one volts which may become a substantial problem in future when a higher definition is required.
The voltage at the pixel gradually decreases until a next addressing pulse arrives (region t2) because of discharge due mainly to leakage current passing through the transistor being turned off. The next pulse is then applied to the addressing line VG. Since the voltage level of the pulse is inverted in this time, the voltage level at the pixel is also gradually decreased to the inverted level in the same manner as described above.
When the addressing pulse is removed from the addressing line, the absolute value of the voltage at the pixel is increased in this case by the voltage drop xe2x80x9cV followed by gradually decrease due to discharge. As understood from the illustration, the voltage applied to the pixel is asymmetrical resulting in several problems such as flicker or deterioration of the liquid crystal material.
Furthermore, it is to be noted that the voltage at the pixel having a waveform of such a complicated pattern substantially tends to vary from pixel to pixel. For example, the rise of the voltage at the pixel in region t1 depends upon the several parameters of the transistor, e.g. the mobility, the channel length, the thickness of the active region, the gate voltage (the voltage applied to the addressing line) and the drain voltage (the voltage applied to the data line). The mobility of the transistor depends largely upon the manufacturing process so that pixel to pixel variation will not be so large. When the panel size becomes large in future, however, it will be the case that the variation within the same panel can not be neglected. Variation in the thickness of the active region may be also a problem in the case of large panels. Variations in the channel length and the channel width are usually as large as about 10% of more from pixels near the driver to pixels apart from the driver.
The voltage drop depends upon the parasitic capacitance of the TFT. The dispersion of the capacitance is about 20% in the case of non-self alignment processes and about 10% in the case of self-alignment processes. Furthermore, since the voltage drop is in proportion to the gate voltage applied, the dispersion of the parasitic capacitance and the dispersion of the gate voltage form a multiplier action to widen the dispersion of the voltage drop.
On the other hand, the gradually decrease of the voltage at the pixel depends largely upon the channel length, the channel width, the characteristics of the active region, of the transistor (TFT). As a result, the voltage level at the pixel fluctuates from solid line to broken line in FIG. 1(B). Particularly accurate quality control is required in manufacturing processes for the devices in order that the dispersion of the voltage at the pixel is always within a tolerable range. As a result, the yield is significantly decreased. It may be impossible to meet future requirements for highly-value-added products with a high yield whereas low quality products may be manufactured with a relatively high yield.
At the present time, a plurality of grades in brightness can be constructed by controlling the voltages at the signals lines. The manufacture of the graded displays seems to be almost impossible even with 16 grades in accordance with the current technique from the view point as discussed below. The threshold voltages of usual twisted nematic liquid crystals are 5 V or therearound, which are divided by 16 into 30 mV for realizing 16 grades. Considering dispersion in the voltage rise at time t1, in the voltage drop and in the discharge, as above discussed, the dispersion of the voltage at the pixel would easily exceed 300 mV unless products are carefully sifted out.
From the above view point, the inventors have advocated digital graded displaying systems in place of analog grading systems. The digital grading are realized by controlling the time for which the liquid crystal is subjected to a driving voltage at each pixel. Details are described in Japanese Patent Applications Nos. Hei3-169305, 169306, 169307 and 209869 of the same applicant. The frequencies required for driving the digital grading displays, however, are 20 to 300 times as high as conventional frequencies so that TFTs of CMOS structure have to be arranged at each pixel in place of NMOSTFT alone. It is also difficult even with such digital systems to suppress disturbance of grading due to dispersion of the characteristics of the TFTs.
For example, when an intermediate grade is selected by limiting the voltage application time only to 45% of one frame, 110% of the predetermined voltage level may be applied to certain pixels whereas 90% of the level may be applied to other pixels, in which case the display incurs 20% or wider dispersion of the driving voltage since 1.1xc3x9745% =49.5% in the former pixels and 0.9xc3x9745%=40.5% in the later pixels. In this case, only 8 grades seems to be possible.
In order to solve this problem, as described in Japanese Patent Application No. Hei3-209870, the inventors proposed for the driving device to collect information about characteristics of respective pixels and input the information into an external memory device. The input data signal are processed in advance on the basis of the information and outputted to the respective pixels in order to make correction. The data processing, however, is so complicated that peripheral circuits must carry heavy burdens. Furthermore, it takes a substantial time to examine the respective pixels and input correction data. For example, if the examination and the data input for one pixel takes one second, the total time of 85 hours is necessary in the case of a panel having 640xc3x97480 pixels resulting in a significantly increased cost.
It is an object of the present invention to provide an electro-optical device (liquid crystal display) suitable for digital grading.
It is another object of the present invention to provide a method of driving an electro-optical device (liquid crystal display) suitable for digital grading.
It is a further object of the present invention to provide a method of manufacturing an electro-optical device (liquid crystal display) with a high yield.
Additional objects, advantages and novel features of the present invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the present invention. The object and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other object, and in accordance with the present invention, as embodied and broadly described herein, in an electro-optical liquid crystal display having a first substrate on which a plurality of electrode pads are formed in order to define a plurality of pixels arranged in a matrix, a second substrate on which an opposed electrode arrangement is formed, an electro-optical modulating layer (liquid crystal layer) disposed between the first and second substrates, and a control circuit for supplying driving voltages to the electrode pads respectively, the control circuit comprises a plurality of addressing lines for scanning the pixels by sequentially supplying an addressing signal to the pixels arranged in each row of matrix to be addressed, a plurality of data lines for supplying data to the pixels arranged in the row addressed by the addressing signal, a plurality of voltage supplying lines for supplying a driving signal to the pixels arranged in the row addressed by the addressing signal and means for selectively connecting or disconnecting the electrode pad of each pixel with a corresponding one of the voltage supplying line in accordance with data supplied from the data lines when that pixel is addressed by the addressing signal. Particularly, the means comprises a plurality of second transistors provided respectively for the plurality of the pixels, each second transistor being connected between a corresponding one of the electrode pads and a corresponding one of the voltage supplying lines and a plurality of first transistors provided for the plurality of the pixels respectively, each first transistor being connected between the gate of a corresponding one of said second transistors and a corresponding one of said data lines, the gate of said first transistor being connected to a corresponding one of said addressing line.
The electro-optical liquid crystal display in accordance with the present invention is particularly suitable for displaying finely graded images. The plurality of pixels are arranged in a matrix and supplied with data signals through the data lines extending in the column direction. Extending in the row direction are a plurality of the addressing lines and a plurality of the voltage signal lines. Each row is selected by activating each of the addressing lines and supplied with a driving voltage from each of the voltage supplying lines.
Referring now to FIGS. 2(B) and 2(C), a typical example of a circuit for controlling each pixel of the liquid crystal display in accordance with the present invention will be briefly explained. FIG. 2(B) is a schematic circuit diagram showing one pixel of the liquid crystal display. FIG. 2(C) is a graphical diagram showing voltage levels appearing at respective nodes of the circuit diagram during operation. The display comprises a number of such pixels arranged in a matrix. A particular column can be made active by activating a corresponding one of the data lines VD whereas a particular row can be made active by suitably activating the corresponding addressing line VG and then the corresponding voltage supplying line VLC.
The circuit for driving one pixel as shown in FIG. 2(B) comprises a first n type thin film transistor Tr1 and a second n type thin film transistor Tr2. The first transistor Tr1 is connected with the data line VD at its drain, the addressing line VD at its gate and the gate of the second transistor Tr2 at its source in order to transfer a voltage level at the data line VD to the gate of the second transistor Tr2 when addressed by the addressing line VG. The source and the drain of the second transistor Tr2 are connected to the electrode pad of a liquid crystal LC and the voltage supplying line VLC. The electrode pad is formed to define one pixel in the liquid crystal.
The circuit operates as follows. When addressed (given a positive gate signal from the addressing line VG), the first transistor Tr1 is turned on to transfer the data level at the data line VD to the gate of the second transistor Tr2. If the data level is xe2x80x9c1xe2x80x9d, the second transistor Tr2 is turned on to supply the pixel with a voltage at the voltage supplying line VLC in order to activate the pixel. On the other hand, if the data level is xe2x80x9cOxe2x80x9d, the second transistor Tr2 is turned off. The voltage at the gate of the second transistor Tr2 is maintained when the addressing voltage is removed from the addressing line VG to address subsequent rows.
In accordance with the above structure, the signal level at the respective data line is not directly transmitted to the pixel so that the timing of the signal operation is significantly relaxed. Namely, even if the voltage level at the respective data line deviates from the predetermined level, the pixel is supplied with a constant driving voltage as long as the deviating level can turn on the second transistor Tr2.
Namely, as discussed above, the pulse width of the addressing signal is extremely short, e.g. 70 microseconds for typical cases, or from shorter than tenth to several-hundredth that of the typical cases for digital grading. The voltage level supplied to the respective pixel tends to fluctuate because of such a short operating time.
On the other hand, it is understood from analysis of the operation of the display in accordance with the present invention that even if the pulse width of an addressing signal applied to the first transistor Tr1 is also very short resulting in variation of the resultant source voltage level, the source voltage is not directly transferred to the pixel but applied to the gate of the second transistor Tr2 instead and therefore is enough as long as its lowest level can control the operation of the second transistor Tr2.
If such conditions are satisfied, a constant voltage can be supplied to the respective pixels from the voltage supplying lines by controlling the on/off operation of the second transistors. Accordingly, the voltage supplied to each pixel is not dictated by the signals from the data lines. The signals from the data lines only determine the on/off condition of the second transistors.
Furthermore, it should be noted that the switching speed of the second transistors may be substantially lower than that of the first transistors. The second transistor can perform its task even if it operates after completion of the on/off operation of the first transistor since electric charge is trapped at the gate of the second transistor Tr2 after operation of the first transistor. Accordingly, the second transistor can be an amorphous silicon semiconductors TFT having a slow switching speed even for digital grading with 32 grades.
Furthermore, the load upon the first transistor of FIG. 2(B) is significantly reduced as compared with that in conventional configurations. Prior to the present invention, electric charge must pass through the transistor addressed within a time shorter than 70 microseconds to the pixel. Electric charge passing through the first transistor of the present invention is accumulated in the capacitance formed between the gate and the drain of the second transistor Tr2. For example, the capacitance associated with each pixel is 30 times as large as that of the capacitance formed between the gate and the drain of the second transistor Tr2 in the case that the area and the thickness of the electrode pad of each pixel are 300 micrometersxc3x97300 micrometers and 6 micrometers respectively and the area and the thickness of the gate insulating film of the second transistor are 10 micrometersxc3x9710 micrometers and 0.2 micrometers. The ratio between these capacitances is furthermore increased to 120 if the area of the gate electrode is decreased to 5 micrometersxc3x975 micrometers.
It will be apparently understood that heavy loads are carried on the transistors in conventional cases. On the other hand, in accordance with the present invention, the load is decreased by a factor of 30 to 120 or more. This means that the switching speed of the first transistor can be substantially increased to 30 to 120 times that in the conventional cases in which digital grading can not be realized with amorphous transistor whose mobility is very low.
The electric charge to be passed through the first transistor, however, is significantly small in accordance with the present invention so that the above problem is not the case. Accordingly, it is possible to drive amorphous silicon TFTs even to realize 64 or more grades. Amorphous silicon TFTs can be produced at relatively low temperatures as compared with polysilicon TFTs, so that massproduction is facilitated to obtain a high yield and reduce the production cost.
The second transistor, on the other hand, can sufficiently perform its task if its switching speed is no lower than one hundredth, preferably no lower than twentieth, that of the first transistor. The amount of electric charge passing through the second transistor is substantially equal to that in conventional cases. Since the switching speed required of the second transistor is very low, however, amorphous silicon TFTs can be employed for digital grading with 32 grades. The switching speed of amorphous silicon TFTs is usually about 70 microseconds which is only 7% of the minimum cycle of the 32 grade digital grading, i.e. 32/32 milliseconds (about 1 millisecond), so that such higher grading can be realized with no problem.
The channel width can be increased for the purpose of increasing the driving capability of the transistor Tr2. Care must be paid in this case because the capacitance between the gate and the drain of the second transistor Tr2 is also increased resulting in a heavy load on the first transistor Tr1. For example, if the channel width is increased by a factor of 5 to obtain 5 times the driving capability, the load on the first transistor Tr1 is also increased by a factor of 5 so that the effective switching speed of the first transistor Tr1 is reduced to 20%.
Referring to FIG. 2(C), a method of driving the liquid crystal display as illustrated in FIG. 2(B) will be described. The addressing line VG and the data line VD are supplied with similar signals as in a conventional display. The signal supplied through the data line, however, is a pure digital 0 or 1 which simply turns off or on the second transistor Tr2. The voltage source line (voltage supplying line) VLC is supplied alternately with a positive signal or a negative signal in synchronism with the addressing signal on the corresponding addressing line VG. The signal on the voltage supplying line, however, is set at O during the time when the addressing line is supplied with an addressing pulse. Reference letters VG to V2 in FIG. 2(C) correspond to similar letters written in FIG. 2(B).
The voltage levels at respective nodes change during operation as follows. The voltage V1 at the source of the first transistor Tr1 (i.e. at the gate of the second transistor Tr2) rises as solid line, then lightly drops responsive to disappearing of the addressing signal and gradually decreases due to discharge through the transistor Tr1.
On the other hand, the voltage level at the source of the second transistor Tr2 (i.e. at the electrode pad of the pixel) changes as follows. First, the second transistor Tr2 is turned on since the source of the first transistor Tr1 rises. Next, since a driving voltage is supplied to the voltage supplying line, the electrode pad is charged to a predetermined level. In this connection, it is noted that since the second transistor Tr2 is already tuned on when the driving voltage is supplied, the charging time is dictated by the one resistance of the transistor Tr2 and the capacitance associated with the electrode pad, resulting in a rapid onset.
The driving voltage is supplied to the voltage supplying line only when a certain time elapses after the addressing signal disappears. Of course, it is also possible to supply the driving voltage just after the addressing signal disappears. When finely grading is performed by means of high speed TFTs as the second transistor Tr2 in accordance with the digital control technique, particularly such a technique as described in Japanese Patent Application Nos.Hei3-183870 to 183873, however, the later alternative timing is not so good.
For example, consider a digital grading with 64 grades. The minimum periodic cycle of the addressing signals is 500 microseconds. Although the pulse width of the addressing signal is about 1 microsecond in the case of a matrix having 480 rows, the first transistor Tr1 can perform its task because of the light load thereon as explained above. There arises no problem, even if the source of the transistor Tr1 rises not so much, as long as the second transistor can be driven. Accordingly, the source of the first transistor Tr1 is considered to sufficiently rise to drive the second transistor Tr2.
In the case that the second transistor Tr2 is designed only to have a switching speed of 70 microseconds, there are formed a number of such transistors with in an actual panel and some transistors among them may have switching speeds as high as 60 microseconds. Such disparity of switching speed originates from production variation such as differences in mobility due to slightly differences in quality of the active region, differences in channel length and channel width due to slight variation of photomasks. In this case, if the driving voltage is supplied to the voltage supplying line just after the addressing signal, some transistor Tr2 having 70 microsecond switching speed is turned on 10 microsecond after other transistor Tr2 on the same panel having 60 microsecond switching speed is turned on. The difference of 10 microseconds is equal to 2% of the periodic cycle of the addressing signal.
The problematic 2% dispersion makes the 64 grades meaningless because the time dispersion of voltage application to the pixels must be limited to 1.6% in order to actually realize 64 grades. Of course, the problematic dispersion can be suppressed by sifting out productions resulting in a high cost to make even the switching speeds. The production cost, however, is significantly increased.
On the other hand, if the driving voltage is supplied to the voltage supplying line when a certain time (80 or 100 microseconds) elapses after the addressing pulse disappears, all the pixels are given the driving voltage substantially at the same time point in each cycle. In this case, the problematic dispersion is dictated only by factors such as the on resistance of the transistor Tr2 and the capacitance associated with the electrode pad. The on resistance and the capacitance are of the order of 1016 ohm and the order of 10xe2x88x9213F so that the time constant is about 100 nanoseconds.
Accordingly, even if the time constant is dispersed from pixel to pixel, the problematic dispersion is no larger than 100 nanoseconds unless the dispersion of the time constant does not exceed 50%, 100 nanoseconds is extremely small as compared with the periodic cycle of 500 microseconds (0.02%) and meets the requirement of within 1.6%. Accordingly, it is effective for finely grading to supply the driving voltage a certain time after the addressing signal disappears.
Similar attention has to be paid when the driving voltage is removed. Namely, a certain time period defining a space duration is provided between the removal of the driving voltage and the application of the addressing signal in order to discharge electric charge accumulated in the electrode pad of the pixel. If the driving voltage is supplied to the electrode pad when the addressing voltage is supplied to the gate of the first transistor Tr1, the electric charge remains at the electrode pad in the case that the data signal on the data line VD is 0 and turns off the second transistor Tr2. In order to avoid such a case, electric charge accumulated at the electrode pad is discharged for the certain time period xcfx84 interposed between the driving voltage signal and the addressing signal. The certain time period xcfx84 corresponds to the time constant as discussed above.
In the next cycle, the driving voltage is inverted. The negative driving voltage is supplied to the drain of the second transistor Tr2 also the certain time period after the addressing signal. The data signal need not be inverted unlike in conventional displays.
As seen from FIG. 2(C), voltage drops are observed only in the gate voltage of the second transistor Tr2. The driving voltage applied to the electrode pad of the pixel exhibits no such variation and no reduction due to natural discharge. This is because the driving voltage is continuously given from the voltage supplying line in accordance with the present invention whereas the voltage at the pixel is supported by electric charge locked by a transistor being turned off in conventional cases. The present invention just features this difference.
Furthermore, broken line is plotted in the figure for the purpose of showing possible poor characteristics of a first transistor Tr1. Namely, because of the poor characteristics, the source voltage can not reach to the drain voltage and is largely influenced by voltage drop when the addressing voltage disappears, followed by a relatively large natural discharge. In accordance with a conventional display having such a transistor, displayed images comprise irregular colors so that the display is not accepted. As seen from the figure, however, the voltage driven by such a transistor can operate with no trouble. Namely, even if the transistor Tr1 exhibits such poor characteristics as shown by broken line, there arise no problem as long as the source voltage can drive the second transistor Tr2.
As seen from the figure, even if the source voltage V1 is lowered as plotted with broken line, no influence appears on the driving voltage at the electrode pad of the pixel. The voltage at the data line is preferably selected in order to guarantee that a most poor one of the first transistors can drive the corresponding second transistor. Of course, the voltage must not be selected to destroy the transistor.
In accordance with experiments conducted by the applicants using small scale liquid crystal panels with 100 pixels (10 rowsxc3x9710 columns), it was very easy to form nine for each ten transistors, functioning as the first transistor Tr1, capable of providing 5 V or higher voltage at its source during operation of the panel in the case that the addressing voltage and the voltage at the data line corresponding to 1 are 15 V and 10 V respectively. The yield was no lower than 95%. In this case, when the voltages applied to the gate and the drain of the first transistor were furthermore increased by 5 V respectively, the yield of the transistors providing 5 V or higher was 99% without no destructed sample.
Experiments were conducted for reference by constructing a conventional type liquid crystal display with transistors having such poor characteristics. As a result, only 60% of transistors could provide voltages at corresponding electrode pads within a range of xc2x10.9 V from the average voltage of 7.2 V. This means that 40% of the transistors were inappropriate even for realizing only 8 grades. When panels were selected in order that at least 90% of transistors met the requirement of 7.2xc2x10.9 V, the yield was significantly decreased. Of course, such experiments were not conducted at best conditions so that it may be possible to improve the result to some extent. The production of more large panel liquid crystal displays, however, is considered to be very difficult.
From the conventional view point, such a configuration having two transistors for one pixel might seem to have adverse affects for increasing the yield. The requirement upon the characteristics of the transistors, however, is significantly low so that the yield is not reduced by the configuration.
The present invention is therefore based upon the concept that if a certain pixel is selected to be active, a constant voltage should be always applied to that pixel. Accordingly, it is avoided that the voltage level at the pixel gradually decreases due to discharge. In accordance with the present invention, the yield is significantly improved as compared with those of conventional analog or digital systems. The displays in accordance with the present invention can maintain a sufficient grading ability even with TFTs having poor characteristics, and as a result the yield and cost performance are significantly improved. It is also advantageous to manufacture displays having qualities no lower than those of conventional displays only with a lower manufacturing cost.
If TFTs are formed by self-alignment processes in the manufacturing method of the present invention, the liquid crystal displays as manufactured become furthermore excellent in operation at high frequencies and in realizing finely graded images. Even if polysilicon TFTs are formed by non-self-alignment processes in the manufacturing method of the present invention, it is possible to display clear images in 64 or more grades without particular difficulties at a cost which is no higher than or significantly lower than that of conventional analog systems capable of 16 graded images. Also even if amorphous silicon TFTs are formed by non-self-alignment processes in the manufacturing method of the present invention, it is possible to display clear images in 15 or more grades at a low cost.